TIMDIS=TIMDIS_0, TIMENA=TIMENA_0, TIMDEC=TIMDEC_0, TIMRST=TIMRST_0, TSTOP=TSTOP_0, TSTART=TSTART_0, TIMOUT=TIMOUT_0
Timer Configuration N Register
| TSTART | Timer Start Bit 0 (TSTART_0): Start bit disabled 1 (TSTART_1): Start bit enabled |
| TSTOP | Timer Stop Bit 0 (TSTOP_0): Stop bit disabled 1 (TSTOP_1): Stop bit is enabled on timer compare 2 (TSTOP_2): Stop bit is enabled on timer disable 3 (TSTOP_3): Stop bit is enabled on timer compare and timer disable |
| TIMENA | Timer Enable 0 (TIMENA_0): Timer always enabled 1 (TIMENA_1): Timer enabled on Timer N-1 enable 2 (TIMENA_2): Timer enabled on Trigger high 3 (TIMENA_3): Timer enabled on Trigger high and Pin high 4 (TIMENA_4): Timer enabled on Pin rising edge 5 (TIMENA_5): Timer enabled on Pin rising edge and Trigger high 6 (TIMENA_6): Timer enabled on Trigger rising edge 7 (TIMENA_7): Timer enabled on Trigger rising or falling edge |
| TIMDIS | Timer Disable 0 (TIMDIS_0): Timer never disabled 1 (TIMDIS_1): Timer disabled on Timer N-1 disable 2 (TIMDIS_2): Timer disabled on Timer compare (upper 8-bits match and decrement) 3 (TIMDIS_3): Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 4 (TIMDIS_4): Timer disabled on Pin rising or falling edge 5 (TIMDIS_5): Timer disabled on Pin rising or falling edge provided Trigger is high 6 (TIMDIS_6): Timer disabled on Trigger falling edge |
| TIMRST | Timer Reset 0 (TIMRST_0): Timer never reset 2 (TIMRST_2): Timer reset on Timer Pin equal to Timer Output 3 (TIMRST_3): Timer reset on Timer Trigger equal to Timer Output 4 (TIMRST_4): Timer reset on Timer Pin rising edge 6 (TIMRST_6): Timer reset on Trigger rising edge 7 (TIMRST_7): Timer reset on Trigger rising or falling edge |
| TIMDEC | Timer Decrement 0 (TIMDEC_0): Decrement counter on FlexIO clock, Shift clock equals Timer output. 1 (TIMDEC_1): Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 2 (TIMDEC_2): Decrement counter on Pin input (both edges), Shift clock equals Pin input. 3 (TIMDEC_3): Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. |
| TIMOUT | Timer Output 0 (TIMOUT_0): Timer output is logic one when enabled and is not affected by timer reset 1 (TIMOUT_1): Timer output is logic zero when enabled and is not affected by timer reset 2 (TIMOUT_2): Timer output is logic one when enabled and on timer reset 3 (TIMOUT_3): Timer output is logic zero when enabled and on timer reset |